Electrical Characterization Of Storage Interfaces In ATOM Based SOCs

Abstract

The amount of Analog circuits in the processor and chipset is continuously increasing due to implementation of complex interconnect protocols which operates at very high speeds. Analog validation of the design block is required for the design team to characterize the behavior of the circuits on the silicon and they should meet the specifcation. As the complexity of the design block increases, the number of tests to be done also increases. The automation of these tests is part of electrical validation and it will effectively reduce the time required in Validation phase of the Product Development Life-Cycle with reduced man power.

In this project effort has been made to enhance the features of electrical validation for storage interfaces i.e. SD, eMMC with combination of python scripts and with prodigy software supported in Tektronix scope. Project includes timing parameters, signal integrity validation and system marginality validation for storage interfaces and also for the PLL and system clocks interfaces .