Reduction of Power in High Speed Control Logic using Automated Design Tools

Abstract

Processor performance is being governed by the ever decreasing chip sizes, in spite of a significant increase in the number of transistors constituting the chip. Designing of the microprocessor block is basically done by two ways a) Data Path, b) RTL to Layout. In Data path we have to do manually synthesis, oorplan, and placement. In RTL to Layout synthesis, oorplanning, placement, clock tree synthesis, routing is done by automated tools. By RTL to Layout ow we can constrain routing till some particular metal layer so that we can save power of the circuit. There are also some tool related commands which can be useful for the design for the synthesis, oorplan, placement, clock tree synthesis, routing. We can also use blockages for the placement of the cells as required. So by RTL to Layout ow way we can reduce the efforts compared to the data path way.