DFT Simulation and Debug

Abstract

Project deals with the DFT Implementation for the Design, test terminology and scan design techniques. It involves RTL level simulations and gate level simulations using Cadence NCSim tool. It involves pattern generation using Tessent TestKompress tool. During simulations I found bugs in the design, so it also includes debugging portion and found the actual reason for problem occurrence. It also involves the understanding of Boundary Scan Architectures like IEEE 1149.1 architecture which is usually known as JTAG architecture and IEEE P1500 architecture. It involves the complete working of TAP controller by its 16 states. It involves the different configuration for programming IEEE P1500 by TAP controller and described the glue logic for those various cases to function the P1500 wrapper and its internal core design. It involves understanding of different Perl scripts related to TAP controller and P1500. It involves wrapper generation and wrapper mapping with the use of some internal tools of ST.