Study And Analysis Of Failure Modes In SRAM Memory and Architecture For Self Correction

Abstract

As the technology is shrinking down i.e voltage scaling for designs is becoming more and more complex, thereby necessitating the need for better and robust architectural designs capable of dynamically detecting and correcting failures.This thesis explores the analysis of failure modes in SRAM read and write circuitry and shows architectural changes done to detect and correct failures.In the project, changes have been made in the read circuitry by replacing single sense amplifier by a dual imbalanced sense amplifier. The changes have been validated on the silicon for a particular test chip using Ocelot Tester in R\&D testing lab.The SMEM(Static Memories)Team is responsible for designing memories at different technology nodes and providing memory solutions to internal and external customers as per requirements.