SoC Development Containing the Teststructures for SiVal of Memories/IO's/Efuses/Standard Cells

Abstract

Systems-on-chip (SoCs) has become reality now, driven by fast development of CMOS VLSI technologies. Complex system integration onto one single die introduces a set of various challenges and perspectives for industrial and academic institutions. Important issues to be addressed here are cost-effective technologies, efficient and application-tailored hardware/software architectures, and corresponding IP-based EDA methods. Due to exponentially increasing CMOS mask costs, essential aspects for the industry are now adaptivity of SoCs, which can be realized by integrating reconfigurable re-usable hardware parts on different granularities into configurable systems-on-chip (CSoCs).

SoC development involves combining different IP's in a single integrated circuit(chip). SoC development infers the advantages like lower cost,re-usability, high performance, high reliability, and reduced chip size. The design complexity and density of a SoC is very high. The design complexity can be reduced by partitioning the system into hardware and software based on functionality. Modelling at higher level of abstractions also helps in reducing the issue of high complexity to manageable level.

The SoC containing test-structures for memories, IO's, Efuse and standard cells is used as test chip for silicon validation. These test-structures containing reticle is used as a reference for development of such structures in a particular process node. The advancement to a particular lower process node will be carried out only if the reticle containing test-structures is successfully implemented. As from front-end point of view the verification of such test-structures is very important and should be thoroughly performed. Several testcases are written to verify the functionality of each module/structure.