Verification Methodologies For Memory BIST

Abstract

The Project deals with functional verification of the MEMORY BIST and supported collar models and controller with an intent to verify all possible modes, application of all the tests by the BIST to ensure desired functionality. Our verification team is responsible for verification of collar and controller models of BIST for all types of memories such as SP-SRAM (Single Port SRAM), DP-RAM (Dual Port SRAM), ROM and BIST Controller as well as all types of supported architectures such as C28FDSOI and M40 NVM architectures. The aim of verification is to establish a common to all and stable verification environment /test bench which can serve to verify all possible configurations of Memory BIST collar and controller. The verification methodologies aim to provide a robust solution to testing and verifying the Memory BIST IP for its given specification covering maximum possible corner cases to deliver an efficient and completely working design.