Next Generation Rtl Simulation Technology For Graphics Design

Abstract

Silicon like behavior at the RTL simulation level is a necessary requirement now days as design complexity increase. Gate Level Simulation (GLS) is useful to achieve this but as design complexity increase it becomes more expensive and time consuming. There are some limitations with System Verilog semantics, one of the limitation is X value simulation semantics. In the first part this report describes this limitation and the enhancement to overcome the problem by next generation simulation technology. System Verilog has several drawback with X value simulation semantics that may be results in simulated X being improperly propagated which in turn may lead to initialization and power related failures in Silicon. Even RTL bugs can be masked and thus RTL simulation may pass incorrectly and would fail at silicon level [3]. System Verilog uses different X semantics for different parts of the design flow. For synthesis X represents Don’t Care Boolean Values (0 or 1), while for simulation it represents an unknown value (0, 1 or Z). Verilog RTL simulation semantics often mask propagation of an unknown value by converting the unknown to a known, while gate-level simulations show additional X that will not exist in real hardware. The result is that bugs get masked in RTL simulation, and while they show up at the gate level, time consuming iterations between simulation and synthesis are required to debug and resolve them [1]. Resolving differences between gate and RTL simulation results is painful because synthesized logic is less familiar to the user, and Xs make correlation between the two harder. Enhancing the RTL simulator for finding X issues will be one of the best ways. This project is about bringing up the new simulation mode on the next-generation servers and graphics design. Second important aspect of this project is improvement in simulation performance by reducing simulation run time & run time memory requirement. There are very big and complex designs and need so much run time while debugging, there is a new debug methodology which gives better run time performance with the same debug capability over existing methodology, second part of the project describes the new debug methodology as a next generation simulation technology.