Design and Simulation of Low Power Low Noise Analog Front End for Digital Hearing Aid

Abstract

About 74% of power is consumed by analog front end of digital hearing aid system Among them 34% power is consume by preamplifier and remaining by Analog to digital converter. Also noise limits the signal level and reduce the dynamic range. So, it is necessary to design low power low noise biomedical systems. To increase battery life, a low power dissipation method is very crucial.

As a preamplifier design, two stage miller compensated operational amplifier is used in sub threshold region for low power dissipation. The graphical method gm/ID Vs ID/W/L is apply for Aspect ratio calculation of MOS transistor. A low noise performance is achieved by selecting PMOS transistor as an input pair in differential amplifier. The gain is changed by selecting di_erent value of input capacitor. The large value of feedback resistor for lower cutoff frequency is designed in weak inversion region The simulated total power dissipation is 2.15uw, open loop gain is 84dB,phase margin is 71’, slew rate is 50kv/sec input referred noise is 3p:2uV /HZ , input common mode range is 0 to 1.7V. the common mode rejection ratio is 98dB and Power supply rejection ratio is 112dB(+) and 87dB(-).The gain is changed from 10dB to 32dB by selecting value of input capacitors. The supply voltage is 1.8V supply with TSMC 0.18um process in mentor graphics.

A First order sigma delta modulator is designed with oversampling ratio of 128, sampling frequency is 256KHz and input signal frequency 1KHz. The power dissipation for First order is 7uw with SNR value 43dB.The total power dissipation is 9uW for preamplifier and sigma delta modulator.