Advanced Processor Architecture Design

Abstract

The aim of the project 'Advanced Processor Architecture Design' is to indigenously design high performance processors. A single-issue, dynamically scheduled, out-of-order speculative processor was first designed. This processor, referred to as the scalar processor aims to execute one instruction every clock cycle. This design was then enhanced to a 2-issue, dynamically scheduled, out-of-order speculative processor. This is referred to as the 2-issue superscalar processor and its aim is to execute two instructions every clock cycle. Both these processors have been developed using the Verilog HDL language in the Xilinx Integrated Software Environment (ISE). They have been tested and simulated using the ISim simulator which is a part of the Xilinx ISE. These processors have finally been implemented on the Virtex-5 Field Programmable Gate Array (FPGA). The implementation on the hardware has been verified using the Chipscope Pro software.

A few simple programs have been simulated on both the processors. These programs have also been executed on the processors, implemented on the FPGA. The results obtained from both these modes are the same. These results are also functionally correct. These results indicate that both the scalar and the 2-issue superscalar processor lean towards achieving their ideal performance of executing one and two instructions respectively, every clock cycle.