Advanced ATPG Based On Fan, Testability Measures And Fault Reduction

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DC Field	Value	Language
dc.contributor.author	Dhare, Vaishali	-
dc.contributor.author	Mehta, Usha	-
dc.date.accessioned	2014-12-09T09:30:29Z	-
dc.date.available	2014-12-09T09:30:29Z	-
dc.date.issued	2014-04	-
dc.identifier.issn	10.5121/vlsic.2014.5202	-
dc.identifier.uri	http://hdl.handle.net/123456789/5238	-
dc.description	International Journal of VLSI design & Communication Systems (VLSICS), Vol. 5 (2), April, 2014, Page No. 11 - 21	en_US
dc.description.abstract	To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The proposed ATPG algorithm is simple and can be used as an open source for academicians. Analysis on ISCAS 85 circuit along with some basic combinational circuits are present for stuck-at faults.	en_US
dc.relation.ispartofseries	ITFEC022-9;	-
dc.subject	ATPG	en_US
dc.subject	Fault Equivalence	en_US
dc.subject	Testability Measures	en_US
dc.subject	ISCAS	en_US
dc.subject	FAN	en_US
dc.subject	EC Faculty Paper	en_US
dc.subject	Faculty Paper	en_US
dc.subject	ITFEC022	en_US
dc.subject	ITFEC010	en_US
dc.title	Advanced ATPG Based On Fan, Testability Measures And Fault Reduction	en_US
dc.type	Faculty Papers	en_US
Appears in Collections:	Faculty Papers, EC

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