Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/5238
Title: | Advanced ATPG Based On Fan, Testability Measures And Fault Reduction |
Authors: | Dhare, Vaishali Mehta, Usha |
Keywords: | ATPG Fault Equivalence Testability Measures ISCAS FAN EC Faculty Paper Faculty Paper ITFEC022 ITFEC010 |
Issue Date: | Apr-2014 |
Series/Report no.: | ITFEC022-9; |
Abstract: | To generate test patterns for the complex VLSI designs, an efficient and simple technique is required. This paper present the development of combinational ATPG based on FAN algorithm, testability measures and fault equivalence. The prime aspect of this work is to develop the ATPG algorithm with less number of faults and testability measures. The proposed ATPG algorithm is simple and can be used as an open source for academicians. Analysis on ISCAS 85 circuit along with some basic combinational circuits are present for stuck-at faults. |
Description: | International Journal of VLSI design & Communication Systems (VLSICS), Vol. 5 (2), April, 2014, Page No. 11 - 21 |
URI: | http://hdl.handle.net/123456789/5238 |
ISSN: | 10.5121/vlsic.2014.5202 |
Appears in Collections: | Faculty Papers, EC |
Files in This Item:
File | Description | Size | Format | |
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ITFEC022-9.pdf | ITFEC022-9 | 817.85 kB | Adobe PDF | ![]() View/Open |
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