Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/5504
Title: Rapid and Compact Generic binary-to-BCD Conversion Circuit for Less Powerful Computational Devices
Authors: Thaakar, Ujjwal
Upadhyay, Darshana
Keywords: Algorithm
BCD
Binary
Conversion
Generic
Computer Faculty Paper
Faculty Paper
ITFIT012
Issue Date: Mar-2014
Publisher: IJCSC
Series/Report no.: ITFIT012-3;
Abstract: Conversion of binary representation into BCD is a very frequently used operation in modern computers due to the exponential increase in the demand for decimal arithmetic. Decimal data processing applications have developed exponentially in recent years thus increasing the need to have hardware support for decimal arithmetic. Most conversion algorithms are fixed bit. we propose an algorithm that is generic and independent of the size of the binary word to be converted.A general purpose algorithm can greatly simplify and unify the process of building BCD conversion hardware implementations at a certain performance cost. This paper illustrates a generic algorithm for converting any n-bit number to its packed BCD equivalent. It is based on an insight into the relationship between a number and its BCD representation. This paper presents novel high speed low power architecture for n- bit binary to BCD conversion.
Description: IJCSC, Vol. 5 (1), March - September, 2014, Page No. 101 - 102
URI: http://hdl.handle.net/123456789/5504
ISSN: 0973-7391
Appears in Collections:Faculty Papers, CE

Files in This Item:
File Description SizeFormat 
ITFIT012-3.pdfITFIT012-373.66 kBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.