Validation of Core RAS features for Intel Xeon Server Processor using Random Instruction Generation Tool

Abstract

Geography is history, human technology is shrinking geographical boundaries, now people can collaborate, access resources present in a remote corner of the world from their comforting bedrooms, offices and on the move, due to the revolution called "Internet of things", cloud computing is gaining popularity day by day. Cloud computing needs lot of storage space, which requires maintaining servers, for storing and manipulating critical data (for example online retail stores, stock markets, investment banking firms, social networking sites, search engines), hence it is imperative that the servers are up and running all the time, and keep the data reliable, and are easily serviceable even after a catastrophe. Intel uses a very through validation methodology, making use of architectural validation technique to spot bugs missed during pre silicon validation, so that the validation cycle can be reduced to achieve product readiness amidst the growing competition. The advanced automation infrastructure maintained in Server System Validation in Intel means that the target under test is continuously bombarded with random test cases to get a 24/7 coverage. The approach in designing validation plan, targeting the areas which were left untouched/ loose ends is explained. Intel architecture uses MCA, to detect, log and recover from hardware errors, which may lead to compromising server integrity and even bringing down the system. RMCA, an advanced version of MCA is discussed at length in this report, the advantages of this approach is that without increasing the cost of hardware, an uncorrectable error can be handled (isolated or resolved) by using the operating system or system software. Pre requisites of loader include for running test cases targeting RMCA are discussed, which includes, setting up the platform, where the Silicon to be tested is mounted, checking the health of Silicon, enabling memory poisoning, and giving the control to the test case, which is self-driven and doesn’t need any OS to operate. Pre requisites of loader include setting up the Machine Check registers to disable error overflow, enabling poisoning of memory, generating complex instructions which will access the poisoned memory location, synchronizing the machine check exceptions across all cores, setting up the handlers for servicing the uncorrectable errors. A case study is discussed in the end to describe the step by step approach followed to debug a failure, from loading the seed to arriving at the cause/ workaround.