Efficiency Analysis on Core Level Validation and Back-End Layout Design

Abstract

Today’s micro-processors contain highly complex and sophisticated design on to a single chip. The higher complexity can increase the bugs in the chip which ultimately affects the functionality of the chip. The complexity in the layout of nanometer scale design also increases the time to market. Therefore, new microprocessors demand efficiency improvement at various stages of VLSI design cycle which can be achieved through automation. The efficiency in VLSI design cycle can be improved at core level validation and back-end layout design.

The pre-silicon validation plays an important role in order to minimize the bugs in the chip design before giving it to the fabrication facility. Pre-silicon validation, a multi-step process, verifies if a chip design sticks to the pre-defined specification and satisfies the designer\rq s objective. The new generation processors demand the high amount of efficiency and coverage in pre-silicon validation.

Firstly, efficiency improvement of core level validation for the three different features AFD (Array Freeze and Dump), PMON (Performance Monitoring) and SMM (System Management Mode) can be achieved through randomization and intelligent algorithms. AFD, the feature of DFT (Design for Testability), compares the expected values of all the arrays of various clusters with its RTL (Register Transfer Level) values at the freeze time and dumps the correct value if the matching is incorrect. The randomization of array freeze and dump in pre-silicon validation helps to check all the arrays in a single test and makes to get closer to post-silicon debug scenario. The performance monitoring monitors the various events at the cluster level and at the core level. To increase the coverage of validating those events in performance monitoring unit at pre-silicon validation, the concept of performance monitoring multiplexer is introduced. This algorithm helps to achieve the coverage of 81.01% with lesser amount of test cases. At last, the automated validation strategy for system management mode is suggested which can help to do debug easier with saving valuable amount of time. All these improvements of the feature validation tries to make the design with minimal bugs before tape-out.

Secondly, the efficiency improvement of back-end layout design is described. The physical design of the chip is one of the important phase in VLSI design cycle. The increment in complexity of physical design of the chip is due to continuous shift towards nanometer scale in the design. Due to some floorplanning and placement changes, re-routing should be required again with respect to new placement of input and output logic cells. These repetitive and manual efforts are tedious and cumbersome.

The proposed automated group routing algorithm exploits modular tile based placement and simplified track patterns effectively. It has reduced routing time by 2x with better control on routing resources and automating the routing at the same time. The algorithm can be improved with merging more physical properties and various design rule checks.

Thus, different strategies like Randomized AFD Testing Mechanism, Performance Monitoring Multiplexer, Automated Validation of System Management Mode and Automated Group Routing Strategy can be used to improve efficiency at pre-silicon validation and at back-end layout design.