Electronic System Level Validation of Ethernet Switch

Abstract

With the increasing level of complexity in digital systems, digital design techniques have advanced and got to a higher level of abstraction that is Electronic System Level (ESL). Designing at the ESL tackles the increasing complexity of System on Chip (SoC) design by raising the level of abstraction in system specification and modelling which also helps to decrease the time to market of the chip. This process involves validating and transforming of the system model with the effective ESL frameworks until the desired level of SoC implementation and coverage is attained. These optimized switches are used, to meet scalability, bandwidth and efficiency demands of the networking environment. This project aims at validating various features at data link layer, network layer and overlay networks of Ethernet switch. These features includes virtualization protocols like VXLAN, NVGRE, etc. Data center applications are no longer bound to specific hardware resources; thus making the application unaware of the underlying hardware and viewing the CPUs, memory, and network infrastructure as shared resource pools. Server virtualization allows the abstraction of server resources to provide flexibility and optimized usage on a standardized hardware infrastructure. Results are analysed for a match with the expected behaviour of the switch. Bugs found in the software model are reported back to the implementation team for a fix and a bug free software model of the switch is obtained for Register Transfer Level (RTL) implementation.