Improvement in Verification Efficiency using Register Abstraction Layer

Abstract

Registers and memories defines software interface to device, and resembles large part of programmer's guide. As registers define HW/SW interface for device, it's very important that register perform as expected for correct operation of design. Thus registers need to be verified through product life cycle. With increased design size and complexity, today's design contains several hundreds to thousands of registers. From specification, documentation to design implementation, verification of each register, each bit and there property involves lot of effort and complexities, which consumes time. Moreover maintaining separate register specification document for each purpose, and manually updating these documents for multiple iterations through product life cycle is error prone and tedious task as number of register increases above few hundred.Use of single source written in high level language like SystemRDL help reduce complexity for generating documents of software, design and verification. Thesis describe a methodology which provides low maintenance, almost zero time maintenance and reusable register design and verification environment. A stable and promising OVM based register verification environment, Register Abstraction Layer (RAL) is discussed. A methodology provides a complete solution form register specification in .xls format to RAL files to reusable verification components and environment. Thesis presents useful RDL constructs for modelling scalable register descriptions, like registers arrays, reg-files and register field instantiation. A sample example for RDL specification helps understand SystemRDL constructs, field, register, and register file and address-map instantiation. Thesis also describes Register Model, lists main components in register model with overview of each. Register Model use flow specified in thesis helps understanding how RAL is integrated into existing environment. At the end results are discussed, for register verification test with use of BFM to replace processor. The results are compared with simulation results of C test run on processor. Result are impressive with 21.46% reduction in CPU time with specified methodology. Also, use of methodology results large improvement in verification efficiency by reducing register verification time from over a month period to week.