SoC Verification of Digital IPs for Automotive Products

Abstract

As we know that semiconductor technology is shrinking day by day, so verification after each step is very important. To deliver a SoC with very less time for design & verification, suitable verification methodology has to be chosen to minimize verification time and to obtain better performance. Verification is involved at each and every step of the designing and developing of the chip so it takes more than 70% time of the total project cycle. An IP (Intellectual Property) is designed and then verified at RTL level & Gate level for its functionality correctness. Automation tools are required to minimize required time for verification of an IP. In ASIC design flow from design to chip tape-out a standard approach is used for SoC verification. In these approaches Hardware Verification Languages (HVL) are use. In new verification methodology system Verilog is used which is based on IEEE standard. To write efficient test-bench, Library and package oriented features are used. Also different approaches of Verification are displayed. UVM based class library gives building blocks used for quickly setup of reusable and well-constructed verification components. Also UVM is used to develop test environments using System Verilog. In the present thesis UVM based development of verification IP of CAN controller is explained. This VIP can be plugged in to SoC level environment. At last Ethernet controller is discussed with PPS pulse generation feature briefly explained.