Low Power Design Techniques for 3D GFX

Abstract

Extremely small chip consuming least power with maximum compute is something market needs. Extreme Graphics compute power became one of the major requirement for many products. Low power optimization techniques spread across architectural, micro-architectural, design and circuit techniques. This requirement pushes VLSI design engineers to keep innovating and finding solutions to achieve same. The main objective of this thesis is to discuss different low power design techniques and there application to 3D Graphics. Clocking circuitry is one of the major power consuming block in any design. This thesis work covers clock gating techniques like active stall, idle stall, etc. some of the data gating techniques and data rearrangement which will enhance clock gating are also discussed. Tradeoff for different techniques is also covered. Shutting down unused logic is another common practice to save power. Power gating comes with verification challenges. This thesis will cover power gating requirements and some of the industry standard techniques to verify crossing of signals across power domain. Caching is commonly used technique to boost up performance by reducing memory accesses. Graphics use caching concept and different caching policies are applied as per requirement, this thesis covers cache basic concept with different techniques and organization. The content addressable memory (CAM) which is used in the RAM or searching the tag value is addressed and new method of searching the tag value using hardware binary search has been demonstrated in this thesis. The implementation of the Hardware binary search algorithm reduces the overall delay in the CAM circuit by 10-20% and we reduced the active encoder size used in the CAM from 1024: 10 to 512: 9. A hardware design for calculating log base 2 and antilog base 2 using piecewise linear approximation is proposed in the thesis which is very fast as compared to the existing log and antilog circuits which uses look up table and this hardware can produce output in a single clock cycle. But this is achieved with maximum error of 0.55% for log circuit and 0.6% in case of antilog and mean error of 0.12% for 1800 samples between 2 and 20 in log circuit and 0.2% in antilog circuit. The log and antilog circuits proposed here is used to build Phong Illumination model which is very basic lighting model in 3D graphics, where these errors in log and antilog circuits cannot be detected by human eyes. The future scope of low power designs are also discussed.