Validation of Mixed Signal IP building Blocks

Abstract

The amount of circuits on the integrated chip is increasing day by day. The Intellectual Property (IP) consist of both analog and digital circuits. These different circuits have to function under the all difficult operating conditions which include wide variation of the temperature, supply voltage and the process variations. The process variation includes the systematic and random variation. The former is due to the resolution limit of the different instruments used during the fabrication of the integrated circuits and the latter is due to variation in density of particles while diffusion and ion implantation. These variations are termed as PVT variations (Process, Voltage, Temperature). Also the circuits must function properly during entire lifetime of the product. So, it is imperative to verify the reliability of the circuits at the extreme difficult condition in terms of fluctuation of supply voltage and the temperatures since these parameter will vary according to ambience. Each circuits in the IP has its own specifications so to simulate its behavior, different kind of analysis like transient analysis, DC analysis and AC analysis has to be carried out. In the reliability analysis we need to evaluate the impact of different phenomena like electro-migration, aging, burn in, Electrical over stress (EOS) for the reliable operation of devices and interconnects of the circuits. The pre-layout and post-layout simulation are carried out independently to monitor the impact of parasitics in the circuits. Since, in the circuit the multilevel routing of metal interconnects is present, the parasitic capacitance will be significant. In the case of multilevel routing the signal integrity and the crosstalk will also play a major role while validating the IP. The power dissipation is also a major concern in today’s era of submicron regime. As the feature size decrease the amount of leakage will be very high in the circuits. The dynamic power dissipation and static power dissipation are of major concern. As the IP is operating at higher data rate (around 6Gbps) the switching activities will be more and that will add to the dynamic power of the circuit. The static power is due to leakage and mostly modeled by sub-threshold current. The process node below 130nm also takes into account the gate tunneling current and the junction leakage current of the transistor. When we are operating the circuits in the extreme corners it is quite necessary to get the value of currents in active and standby mode. In these corners supply voltage and temperature are at their peak values and the skew is fast. At this corner the value of current will be maximum. The different model files are available from foundry which is the information of process variation data based on statistical analysis performed over the die by the process engineers. Depending on these data and application of circuit the cross skew analysis is also performed. In the cross skew analysis one device will be faster and its counterpart will be slower. Since the doping step is different for nMOS and pMOS the cross skew corners exist.