Bit Cell Architecture For Embedded Rom

Abstract

In recent microprocessor designs Register File (RF) and Read Only Memory (ROM) arrays comprise over 50% of the total core area. The On die ROM usage is increasing as there is an increased focus on IOTs, multi-core microprocessor for notebooks, 2-in-1s and mobile applications. ROM memories are used extensively to store the fix information, such as micro-codes for complex micro-operations in the micro-processors, or as the data coefficients which are used in digital filters. Reduction of active power and leakage power in ROM memories has become more important, because of the use of power constrained design and as an addition to it the design which provides high-performance has increased, and also for the low-power portable systems, such as cellular phones and notebooks, which requires a longer battery life are also the necessity of this generation high-speed use. Achieving high performance at low power specification need considerable innovation. Use of High Threshold Voltage (Vth) devices may not be the solution when targeting high performance designs. Further, as technology scales, leakage increases exponentially, which requires more aggressive low power (low leakage) schemes. The leakage power component constitutes a big part in the total power consumption in conventional ROM circuits. This paper describes a proven ROM architecture that reduces significantly leakage, without speed decrement and area penalty.