Front-end ASIC Design and Verification of Programmable and Precision Delay Timing Generator for CCD Detectors

Abstract

Charge Coupled Devices (CCD) work by converting light into a pattern of electronic charge in a silicon chip.CCDs have features like high sensitivity, high linear dynamic range, electronic shuttering capability and low dark current.Various CCD architectures like linear array, full frame, interline, TDI, etc. are used for various application.One of the main unit in a CCD based satellite imaging system is Timing Generator producing various kinds of readout clocks and control signals for different CCD architectures. This Project discusses about the front-end ASIC design of programmable and precision delay timing generator for various CCD architectures. Various CCD requires different types and number of clocks for its operation. The aim is to provide flexibility in terms of number of different types of clocks, effective image area, read out feature and a very precise delay control for each clock. Programmable clock generation with precise delay is implemented with an all digital Delay Locked Loop (DLL) because of its features like low power, smaller area, high noise immunity and synthesizable circuit. Precise delay resolution in sub nano seconds (approximately 620 ps) is obtained at clock frequency of 20 MHz. Programmable pulse generation logic is designed which can generate pulses with variable frequency and with variable pulse widths. The design is targeted with 180 nm technology. A single chip can cater to support various CCD architectures with full programmability. Assertion based and coverage driven constrained random verification of precision delay timing generator is carried out using system verilog.