Advance Automated Mechanism for Design, Compilation Verification and Validation Flows of Complex SoC Design

Abstract

Time-to-market is one of the key factors for any company to release its product and get hold on customers. The designing part should be completed in a short span of time so that verification and fabrication can be completed without missing technology window. The design steps and software tools required on the front end part for designing modern systems-on-chip are no longer adequate for the complex systems of today. VLSI design process which involves writing RTL, compiling and verifying it are time consuming, verification itself consumes 70% of the design time. Regardless of using a lot of CAD tools for the VLSI design, the process looks very complex and requires a lot of efforts for managing and verifying the design. To handle this complexity different tools and flows are been developed to reduce the time required for design and verification, where the inputs required for the tool are generated by the flow. Verification gets easily done if the flow is tool friendly and generates all the required files by tool in proper format. This report details about advance automated mechanism used for frontend design and verification through which time required and the complexity of frontend process can reduced. Advance mechanism is a converged front-end flow that is flexible and easy to use. It supports all the modern design and verification methodology like formal verification, functional verification, design linting, static timing analysis, low power checks, emulation etc. it is generic and encompasses different VLSI flows. A higher degree of design confidence and reduction in the risk of re-spin or repeated efforts is the main aim of the advance system. It also provides a common environment to many projects while providing project-specific customization. This report also details about modern and efficient methodology of formal property verification for design verification. It is observed that design data and verification and debugging time reduces significantly by using formal methodology for verification.