Analysis and Characterization of Low Power SRAM Memory Compiler

Abstract

Designing embedded SRAM memory with optimum power consumption and minimum area is very challenging task as far as VLSI is concerned because there is always a trade off between power, area overhead and performance while carrying out block level designs in VLSI. In order to improve the performance of the processor one should use an optimum size of SRAM with low leakage bitcell and periphery devices in static condition.This report, include the design-analysis and characterization of the SRAM low power techniques in the standard cell environment. After introducing half swing pulse mode and divided & hierarchical bit-lines method access time reduced up to 10-12% and power consumption reduced up to 25-30%. The characterization of the source biasing for bitcell is enhanced method of source boosting method to save the bitcell leakage but area penalty is a major concerned in both methods. The low power modes save a leakage in periphery part upto 8-10% as far as static condition is concerned. The peak power issue is a very critical constrain while analyse the taller SRAM memory instances, for that introducing the control chain mechanism to reduced peak current up to 22-24% also include the design aspect of bitcell and sense amplier with 90nm TSMC bitcell model, 32nm scaled version from 90nm and 32nm 1-D scaled version from 90nm.