Assertion based Verification of STBUS

Abstract

As technology advances, design size and functional complexity increases. Thus, the effort required to verify chip also increases even more faster rate. Thus, verification of chip with high density and functionality is a very time consuming due to elusive bugs and functional verification complexity. It is estimated that over 70% of design cycle for any new design is spent in the verification process. Assertion based Verification improves design quality and verification productivity. Here, 94 SystemVerilog Assertion Checks are added in Verification IP of STBUS (a widely used bus protocol from STMicroelectronics) for Simulation based Assertion Verification. From them, 100% assertions are covered, all assertions passed and none failed.