Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/6268
Title: | Automation and Optimization in Memory Generators |
Authors: | Patanwadia, Krunal |
Keywords: | Computer 2013 Project Report 2013 Computer Project Report Project Report 13MCEN 13MCEN08 NT NT 2013 CE (NT) |
Issue Date: | 1-Jun-2015 |
Publisher: | Institute of Technology |
Series/Report no.: | 13MCEN08; |
Abstract: | We automate the flow of memory generate for the user. User provides set of configuration on basis of that we build a product for them. We work on different technology such as 14nm, 28nm, 45nm etc. Within each technology we have different compilers such as ROM, Hiperf RAM, Loleak RAM etc. and for each compiler we generate different cuts.Cut mean Configuration for single memory. We can generate this memory (product) in two ways: 1) Layout view. 2) Netlist view. Here we will mainly focus on Layout view. How the whole process follows to generate a product. We will see two approaches to generate memory and see how time is saved. We will generate cuts by using basic cells and generate whole memory as per User’s requirement. Once the product is created we have to validate this product and for validation we have to run the simulation on all possible different cuts where input option changes. |
URI: | http://hdl.handle.net/123456789/6268 |
Appears in Collections: | Dissertation, CE (NT) |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
13MCEN08.pdf | 13MCEN08 | 1.49 MB | Adobe PDF | ![]() View/Open |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.