IR @ Nirma University
Keeping in tune the global developments we are creating an institutional repository using DSpace Software (Digital Library Software). We are archiving institutional knowledge like, faculty papers, theses, and dissertations in PDF format at DSpace. Students can access this digital information anywhere in the campus.
Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/6371| Title: | Low Power Testing Architecture in Built-in Self Test |
| Authors: | Parmar, Harikrishna Mehta, Usha |
| Keywords: | Scan Matrix Low Power Testing BIST ATE EC Faculty Paper Faculty Paper ITFEC010 |
| Issue Date: | 9-Dec-2010 |
| Publisher: | Institute of Technology, Nirma University & IEEE |
| Citation: | 1st International Conference on Current Trends in Technology, NUiCONE 2010, December 9-11, 2010, Institute of Technology, Nirma University, Ahmedabad |
| Series/Report no.: | ITFEC010-26; |
| Abstract: | Reducing power dissipation during testing is becoming necessary for decreasing the risks of reliability problems and manufacturing yield loss. So test power has been major big concern in large System-on-Chip designs from last decade. In this review paper, Several architecture have been proposed for reducing power dissipation during BIST. The paper contains the detailed survey on various power reduction techniques proposed for scan architecture. |
| URI: | http://hdl.handle.net/123456789/6371 |
| Appears in Collections: | Faculty Papers, EC |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| ITFEC010-26.pdf | ITFEC010-26 | 247.45 kB | Adobe PDF |  View/Open |
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