Memory Flow Generation and Validation

Abstract

SoC chips are designed using IC design cycle. And Memory Layout design is an im- portant step in the design cycle. It aims to generate various representations of memory cells, called views, which are used by diferent vendor tools for designing memory. Earlier, it took around 10-15 months to generate memory layout with given specifications and technology. To reduce this time, memory generators were developed which can easily generate layout for a given technology with diferent specifications. To generate any layout, the generators need corresponding package of products and the layout thus gen- erated needs to be validated. Further, layout validation is a resource-intensive process and could not be carried out on local machines and thus require to be executed on cluster of computers with availability of load balancing service. This dissertation report focuses on automation of product compilation into package, monitoring generations launched on cluster computers and generating job execution statistics to analyze their performance. A scalable approach has been proposed for product compilation which overcomes the limitations of previous approach. New scripts have been written for monitoring generations verified with suficient test cases. Scripts for generating job statistics have also been written and put to implementation.