Random Stimulus Development for Asynchronous Events of an Armcore

Abstract

Functional verification is a key aspect in verifying microprocessors.Manual verifica- tion doesnt ensure all Architectures have been verified with all possible corner cases. The rapid development in microprocessors demand a fast and automatic stimulus generator which ensure to meet the given constraints and randomly produce enormous numbers of stimulus for functional verification of processor.The generator should be smart enough to take constraints from user and try to generate the feasible,random stimulus depending on underlying architecture.The generator should be aware of the limitations of micropro- cessor architecture and should incrementally generate the stimulus depending upon the current state of the microprocessor RTL state. The proposed work is to develop random stimulus and associated environment for asynchronous events like interrupt and abort.