Testchip Design And Verification Automation

Abstract

Purpose of TestChip is to verify the invented Technology and IPs added in System On Chip(Soc) which implementation in silicon wafer. It includes all the IPs which are to be used for Researched Technology or System On Chip(SOC) applications. TestChip provides post silicon validation details included Library of Memory,RO,Standard-Cell,Analog or any other IP. Before any SOC/ASIC Mass Productions, Test Chip gives us better silicon parameters and testability. Test Patterns are similar to test vectors except these are cycle based patterns. Patterns for the testing are deliver to the Fabrication after the tape-out. These Patterns are almost same except which IP are being tested so that to make these patterns automatically gen- erated. Fulfillments of this tool gives better quality of test patterns,accurate and less time consuming to generate. It also helps in quick verification of RTL/netlist of any block or while chip. RTL Generation is Generating Register Transfer Logic(RTL) of the multiple block in less time period. To make Register Transfer Logic(RTL) of the BLOCK automatically generated. They already have one automation for this but its using XML language for generate the Register Transfer Logic(RTL). When tool crash because of the lack input and any other reason its hard to debuge by designer. So develop one tool which is using tcl language for generating Register Transfer Logic(RTL). This thesis presents a test chip methodology and automatic generation of test pattern and Register Transfer Logic(RTL) to help achieve fundamental goals.