Development of Accelerated VIP of AMBA APB and AXI Protocol

Abstract

The continuous improvement in design methodologies and processes has made possible the creation of huge and complex design system. At the same time, reduced time to market does not provide the sufficient time to make the design completely bug free. The verification engineers need to verify the design in minimum amount of time so that the chip is produced within the time to market period and that too keep the amount of error as minimum as possible. The existing verification techniques ensure a correct Intellectual property (IP) but a coverage driven verification (CDV) is always preferable that uses functional coverage approach to minimize test cases and hence improve the verification process. As the designs are pushing towards reusable environment so must the verification environment. Verification takes almost 70% of design time, therefore verification engineers need to use same reusable verification environment so that verification does not become bottleneck. That is where the concept of VIP comes. In built tests gives jump start in achieving desired coverage goal. UVM (Universal Verification Methodology) introduce a reconfigurable and scalable platform to facilitate a high reusability both in IP level and SoC (System on Chip) level subsystem. UVM supports generation of constraint random stimulus to hit corner case of the design under verification (DUV) and bus protocol based design to create high level test benches that are adaptive and reactive. Sometimes chips are too big to verify with simulation. Simulating a design with millions of logic gates requires hardware assisted verification environment that is Accelerated Verification Intellectual Property (AVIP). Dual top environment enables high speed achievement that is hundreds to thousand times greater than what we had with normal simulation. AVIP makes hardware assisted verification easier and more productive by separating timed and untimed tasks on software and hardware respectively.