Please use this identifier to cite or link to this item:
http://10.1.7.192:80/jspui/handle/123456789/6924
Title: | Standard Cell Design And Libraries Development |
Authors: | Waghide, Aniket |
Keywords: | EC 2014 Project Report Project Report 2014 EC Project Report EC (VLSI) VLSI VLSI 2014 14MEC 14MECV 14MECV02 |
Issue Date: | 1-Jun-2016 |
Publisher: | Institute of Technology |
Series/Report no.: | 14MECV02; |
Abstract: | Standard cells are the building blocks of the modern ASIC world. They can be thought of as the alphabet that allows the ASIC designer (or ASIC design team) to write the novel (that is, design the ASIC). They consist of several simple (in general) functions, usually in various strengths, that can be (potentially repeatedly) connected together in a network and then patterned on a piece of silicon, such that the result is a desired functional integrated circuit. Digital design kit (DDK) vendors, most often representing fabrication houses, usually offer them in a family of several hundred of the various functions and strengths. The actual choosing of which standard cells in a family to use in a design and the actual placing of these at various locations on a piece of silicon, both of which can be done manually, is usually done by software provided by various engineering design automation (EDA) vendors. These various software tools, work with representative aspects of the various standard cell that are pertinent to the particular software’s requirements in order to perform properly their specific function. |
URI: | http://hdl.handle.net/123456789/6924 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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14MECV02.pdf | 14MECV02 | 3.26 MB | Adobe PDF | ![]() View/Open |
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