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Title: | Development Of Utilities To Measure Effectiveness Of Tests Generated By MP RIS Tool |
Authors: | Pandit, Vivekkumar |
Keywords: | EC 2014 Project Report Project Report 2014 EC Project Report EC (VLSI) VLSI VLSI 2014 14MEC 14MECV 14MECV13 |
Issue Date: | 1-Jun-2016 |
Publisher: | Institute of Technology |
Series/Report no.: | 14MECV13; |
Abstract: | In the realm of verification, Random Stimulus Generation or Random Instruction Sequence (RIS) is widely recognized as an effective approach for verifying corner cases that are difficult to anticipate. While most of design bugs are detected by the deterministic formal approach, RIS is highly effective in hitting corner cases. This dissertation report contains the project work of the utilities that were developed for MP RIS tool used for verifying processor coherency. These utilities developed to make an MP RIS Tool capable of measuring the test efficiency and also provides feedback to ensure that verification intent for a given target verification area was met. These utilities have been rolled out along with the RIS tool. The first utility was targeted towards generating corner-case test sets for floating point operation verification. Here an interface is created that the RIS tool could call to generate test-sets, with which the registers would be initialized before performing the desired FP operation. This approach uses random constrained approach, where the exponent is subject to certain bound taking into consideration the precision which determines the floating point format. The randomness ensures that the generated test-sets cover as many points in testing space. The second utility created with the aim to help in the analysis of cache-line migration/intervention events in Multi-Processor verification. One of the key aspects to RIS based MP verification is the ability to generate collision events from different cores to the same region, which can have a cache-line based granularity or page granularity, in a false shared manner. These collision events will ensure that cache lines migrate within the private/local caches of the different processing elements. In this work, a utility called HeatMap is developed, which parses the simulation traces and graphically depicts the collision events to regions that were accessed within a test from the different processing elements. This utility also acts as an additional QA check, to ensure that intent of verification was met. The third utility helped in the quality assurance (QA) of the tests generated from the RIS tool, with some basic checks like memory page info, exception check and incompatible attribute check. |
URI: | http://hdl.handle.net/123456789/6934 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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14MECV13.pdf | 14MECV13 | 1.39 MB | Adobe PDF | ![]() View/Open |
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