Power And Signal Integrity Of Asic Design

Abstract

Physical Implementation of any ASIC design is process of converting Register Transfer Logic (RTL) design to routed gate level netlist considering provided constraints and targets for timing closures. Implemented design also has to meet power specifications and Design Rules. After successful implementation of the design, it can be fabricated on the silicon and ICs can be made. Physical implementation of any design follows a flow which is called physical design flow or RTL to GDS-II flow. This flow divides implementation in small steps like floor planning, placement, power planning, clock tree building, routing, etc. Design closure in advanced designs requires a delicate balance of many complex issues. Timing remains critical, but power has become important toward achieving design success. Today, power management is a mainstream design challenge and a key concern for chip designers as it affects packaging decisions, cooling requirements, battery life, design performance, and chip reliability. Power, timing, and signal integrity (SI) effects are all interdependent at 90- nanometers (nm) and below. To achieve the highest accuracy power analysis, an accurate timing engine is required to perform accurate timing and slew calculations. Since timing parameters affect power dissipation, designers require a solution that takes advantage of these inter dependencies. Due to large power densities, smaller voltage supplies, and higher frequencies, full- chip dynamic and static power integrity is one of the key challenges for designs. Dynamic power and peak voltage drop is difficult to analyze and correct, being a transient phenomenon and its impact on chip timing and yield is a growing concern.