Highly Optimized 2-Step Design Validation and Integration System Delivery to a Multicore Project

Abstract

With the rapid growth in semiconductor technology, always in alignment with Moore’s prediction, the designers face large integration capacity than they can consume. Furthermore, the cut throat competition in electronic innovation is constraining the designers more and more to minimize the time and meet the "time to-market" window. Without change and evolution in the design process and testing process, it will not be able to simply reduce reasonable amount of time. One possible methodology to reduce this productivity problem is the "design-reuse", which consists in the re-exploitation of the already designed modules in different context, well-known under the name of IP-reuse. In the concept of IP reuse, the IP module is once compiled individually and then with the entire SoC modules, thus it is being validated twice, leading to the concept of 2-step compilation. This report details about compilation flow used for front end design and verification through which time required and the complexity of front end process can be reduced. In Intel earlier different design teams used their own legacy flows. A new flow was proposed which was a mixture of all the flows and can be used many design teams. Advanced Streamlined System (AS-2) is a mixture of the legacy flows used for validation of the SoC or design modules. It also provides a common environment to many projects while providing project-specific customization. Flows that were used earlier for validation of the IP’s were not compatible with today’s generation SOC’s. Advanced Streamlined System is converged, 2-step but it has performance gap and integration bottlenecks. Performance analysis of the current system is done to reduce the time for validation in best possible ways and finally flow migration to the new highly optimized system.