Delay Locked Loop For High Speed Serial Interface

Abstract

The performance of high-speed wire-line data links depend crucially on the quality and precision of their clocking infrastructure. With aggressive scaling of device susceptibility of signal to process, voltage, and temperature variation increase tremendously. Because of high speed and low power design timing and voltage margin reduce respectively. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design trade off in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. Digital communications technology as well as integrated circuit scaling trends has enabled the industry to dramatically scale the bandwidth of high-loss networks such as DSL and Ethernet. Many of these networks are channel bandwidth limited and have had to leverage sophisticated equalization techniques to push well beyond the uncompensated channel bandwidth. Proper clocking architecture dramatically reduce burden on sophisticated equalization technique for generating a high bandwidth on and off chip link .so tradeoff between power, performance and area (complexity) can solve by proper handling of clock through distribution. Delay locked looped provide easy means of phase synchronization of sampling clock and data. Due to optimum sampling point in time-domain decision threshold get extra tolerance against noise, inter symbol interferences, jitter, and skew. All digital delay locked is presented here with wide frequency range, small locking time, less jitter and stable phase of delayed clock. Two types of delay line coarse delay unit and fine delay unit together provide a wide delay regulation range and finer delay resolution. Bang-bang phase detector with delay less than clock period enable us to update delay value at each clock cycle hence time to lock improved.