Accuracy And Runtime Improvement Techniques For Power Characterization Of Compiled Memory Arrays For Soc Platforms

Abstract

With the advent of increasingly complex systems, the use of traditional power estimation approaches is rendered infeasible due to extensive simulation times. Hardware accelerated power emulation techniques, performing power estimation as a by-product of functional emulation, are a promising solution to this problem. However, only little attention has been awarded so far to the problem of devising a generic methodology capable of automatically enabling the power emulation of a given system-under-test. In this paper, we propose an automated power characterization and modeling methodology for high level power emulation. Our methodology automatically extracts relevant model parameters from training set data and generates an according power model. The number of memory instances per chip is increasing rapidly. To support the full range of process, voltage and temperature corners (PVTs) and the sensitivity to process variation, the number of data points per characterization run is growing exponentially. For dynamic power and leakage characterization, the advantages of proposed technique over the existing flow are capability to simulate bigger memory blocks, faster post-layout simulation and 30x runtime improvement when compared to existing solution with 0.8% accuracy trade off.