Design and Simulation Of Different Architectures Of Analog Multiplier Using Sub-Micron Technology

Abstract

The four-quadrant multiplier is a very important building block of analog signal processing system. It has many applications in automatic gain controlling, phase locked loop, modulation, detection, frequency translation, square rooting of signals, neural networks and fuzzy integrated systems.It performs linear product of two continuous signals x and y, yielding an output z = Kxy, where K is a constant with suitable dimension. The linearity, speed, supply voltage and power dissipation are the main metrics of performance.At present, the power consumption is a key parameter in the designing of high performance mixed-signal integrated circuit. The main objective of this project is to analyze different architectures of analog multipliers. In this report basic types of analog multiplier architectures such as wide range analog multiplier,multiplier based on nMOS transistor,multiplier working in triode region are presented, which is widely used, and a new architecture is proposed and their performances are compared by ac analysis, dc analysis, and transient analysis,linearity error. All multiplier circuits are implemented with 0.35-μm CMOS technology with power supply voltage of 1.5V and simulated using BSIM3 modeling parameter in T-Spice(Tanner EDA) and Eldo (Menter Graphics).