SPI NAND Memory Model Development and Verification

Abstract

In industry, memory is the basic requirement for permanent or temporary storage of data. Memory models which have superior write performance and high storage capabilities are more likely to be used. Among the various memory models, SPI NAND Memory Model is widely used. NAND memory model provides high storage capabilities and SPI is the interface which is used to provide superior write performance. The developed SPI NAND memory model needs to be compatible with respective controller core, for which verification process is used. verification process related to the verification of those particular specifications and features which are recommended by the customer. Processes like regression, functional verification are used to ensure the compatibility of the memory model with the memory controller core. In this thesis, SPI NAND Memory Model is developed and verified. The whole thesis is divided into two parts; one is the development of SPI NAND Memory Model and second is Verification of developed model. Development process required the knowledge of VIP architecture, and programming language. VIP architecture consists foundation libraries, script _les, core C code, simulator interface, and their functionality. Programming languages like; C, Verilog, System Verilog, Specman, e, SystemC, and Vera can be used to develop and verify a model. Ethernet VIP was tested using System Verilog in initial phase. Verification starts with preparing test plan, which contains list of different test scenarios required to verify particular feature of developed model. Features of SPI NAND Memory Model like; PAGE READ, PAGE PROGRAM, BLOCK LOCK, BLOCK ERASE, RESET, etc. are successfully verified using Verilog.