Design and Analysis of Power Efficient Dual Rail Methodology

Abstract

As SoC, Analog IP’s and Digital IP’s require memory to store the data, which occupy 50- 60% area on chip so memories are major part of subsystems e.g., embedded SRAMs, and register files Memories. The Memories becomes a most critical component for the SoC Design because of mainly leakage power consumption saving of memory limited by threshold voltage scaling. In memory, it is not possible to operate beyond 0.6V due to SNM issue. The static random access memory(SRAM) macros are designed for two different power supply voltages. An memory array is connected to first power supply and a pre-charge control is connected to the second power supply voltage. Also the precharge control is coupled to a bit line through a bit line pre-charge. The voltage level of both power supply equating by introducing level shifter in between both the power supply. So this methodology separates the supply voltage for array and periphery logic is known as Dual Rail Methodology.