Functional Verification of Local Move Link Sub System at Module Level

Abstract

The gate counts and system complexity growing exponentially, with that engineer confront the most perplexing challenge in chip design cycle: Verification. Verification of the design RTL is done at various phases of the chip design flow at different abstraction levels. The Major Project traverses through the chip design flow and functionally verifies the module of the chip. This is done at low abstraction level concentrating on the core functionality of the module. The inputs to module are forced through the testbench and its interfaces are not looked upon. This is the functional verification of chip at module level and is done at the RTL design phase. The designer updates the RTL as per the feedback. After the RTL is been finalized after fixing all the bugs, it is send to the fabrication unit. The chip under functional verification is a tester instrument chip, which had various blocks like Timing Generator block, Memory Pattern Generator block. To verify the Timing Generator block and Memory Pattern Generator block verification environment had to be developed around these blocks. So the Environment should me very generic and flexible in order to verify all different kind of blocks in the chip. Various test cases were developed to cover all the necessary features of the blocks. The test cases were fired and the waveforms were analyzed to debug the RTL as well as test bench issues. Once all the test cases are passing, code coverage is done using a code coverage tool. The code coverage results are analyzed to uncover any dead code as well as logic which were never exercised. The main objectives are to learn the fundamentals of chip verification as well as ensure functional correctness of blocks under verification from Environment to final coverage against their specifications. The block to be verified is Local Move Link. To exercise the modules for their core functionality test cases are to be written and simulated based on the features. The failing tests have to be debugged for any RTL issues and once the design is stable daily regression are to be carried out with random seeds to make sure that the designs are bug free. At the end Code Coverage is to be carried out to reach to each and every hidden corners of RTL and based on it new test scenarios are added.