Identification Of Validation Collaterals Using Architecture Specification

Abstract

Enhancements in technology, to some extent, have empowered the progress of multi-million gate designs from very large printed circuit sheets to small-sized processor chip. With the consistently expanding complexities and contracting geometries, the difficulties with processor configuration have developed significantly. The expanded complexities of processors have provoked the need of increase in design, functional and performance verification efforts to meet the client and time-to-market demands. Thus, the traditional verification techniques no longer satisfy the needs of verifying complex architecture as a whole. Hence, it is necessary to upgrade the techniques for effectively carrying out the verification so that it can cover all the corner cases and analyse them if the given architecture design or instruction set behaves as per the expectations. AVS is widely used test suite for carrying out verification of the ARM architecture. The grounds of verification or the parameters serve as the basis for carrying out any verification or validation. This report will be describing the steps to be performed prior to the verification process and also the motivation behind it. It also describes the verification technique that is conducted at ARM. The report will also describe my contribution in the verification flow or methodology.