Placer Tool for Reconfigurable Logic Blocks on eFPGA

Abstract

The Training Semester from 15th September 2008 has given me an opportunity to work with one of the best semiconductor companies in the world, STMicroelectronics. PiCoGA is STMicroelectronics Specific FPGA Chip which is an acronym for Pipelined Configurable Gate Array. The PiCoGA is designed to implement a peculiar pipeline where each stage corresponds to a piece of computation, so that high throughput circuits can be mapped. In this way a sequence of PiCoGA instructions can be processed filling the pipeline in order to exploit parallelism. Along with this the configurable unit also preserved its state across instruction executions. A new PiCoGA instruction may directly use the results of previous ones, thus reducing the pressure on the register file. Moreover a tight integration in the processor core gives the opportunity to use the PiCoGA in many different computational cores. With the arrival of PiCoGA, the problem of multi-computing was solved to achieve a much faster computation. The main goal of this Dissertation is to Design a CAD(Computer Aided Design) tool which perform the placement of Reconfigurable Logic Blocks on eFPGA, address the challenges occurring because of the different constraints due to the architecture of chip.