Layout Design of I/O Blocks in Latest CMOS Technologies

Abstract

The nanometer era has revealed significant concerns in physical effects, which are now the leading factor in the failure to achieve acceptable yield. A combination of factors that emerge in nanometer scale IC’s, such as shrinking feature sizes, finer line widths, longer interconnect and more routing layers have a profound effect on the ability to gain acceptable levels of yield. Today the I/O structures probably require the most amount of circuit design expertise along with a detailed process knowledge. It is the I/O element which finally interface the core signal to the off chip environs. Thus however efficient the core design may be, it is the I/Os which determine the efficiency of the chip. The basic fundamentals of Input/Output chip design which comprises of Input buffer and Output buffer are discussed. The several other internal circuits involved such as Slew Rate Control, hysteresis, Level-up shifters, Level-down shifters etc. have been discussed in detail with the respective pads. The technology 28nm FDSOI is used in designing the IO layout in Cadence Virtuoso Layout Design tool. Layout Design of I/O blocks gives the detail information in designing a layout with the constraints to be taken into care and the guidelines for making layout has also been discussed. The Physical Verification tool is used by every major foundries to develop the design rules in order to ensure acceptable design performance in new process technologies.