Hardware Based Implementation of CCSDS Formatted Data Packets

Abstract

In the field of satellite-based Data Reception, two major parameters, rate, and quality of data transmission are required to meet standard. CCSDS (Consultative Committee for Space Data System) is a protocol for satellite Data Communication. CCSDS standard allows configuring the rate and quality of data transmission across various platforms of a satellite. It de nes the implementation for data exchange, in addition to facilitate interoperability between satellites as well as the satellite to ground station.In order to support CCSDS in ground segment, the overall require- ment can be split into two broad categories, namely (1) Real Time Data Acquisition and (2) CCSDS Prescribed Processing. The project is targeted to implement the CCSDS protocol in the ground segment using the FPGA-based real-time platform at 50 MHz. CCSDS processing typically comprises of Attach Sync Marker, Randomization and Reed-Solomon(RS) Encoding at the transmitter side and the Frame Synchronization, De-randomization and the Reed-Solomon Decoding and the Data acquisition System at the receiver side. The Real Time data Acquisition is continuous DMA(Direct Memory Access) of decoded data of satellite and sustained transfer to the host. Here the blocks of CCSDS at transmitter and receiver side are designed, simulated and implemented using VHDL. The hardware platform used is Xilinx based Zynq Soc (Z7020) and the simulation is carried out using Xilinx VIVADO. The real-time data acquisition system is im- plemented using the built-in ARM core of Zynq. The testing of Transmitter side is carried out by implementation of ramp pattern of 50 MHz. It is given as an input of RS encoder and generates the parities for error correction of transmitted signal. At the receiver side encoded data is given as an input of decoder. For the testing of data acquisition system AXI IP of Ramp generator is implemented and that is given as input of AXI DMA.