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http://10.1.7.192:80/jspui/handle/123456789/8563
Title: | FPGA Implementation of Digital Beam Former for Synthetic Aperture Radar (SAR) Application |
Authors: | Dohare, Parul |
Keywords: | EC 2015 Project Report Project Report 2015 EC Project Report EC (VLSI) VLSI VLSI 2015 15MEC 15MECV 15MECV08 |
Issue Date: | 1-Jun-2017 |
Publisher: | Institute of Technology |
Series/Report no.: | 15MECV08; |
Abstract: | This thesis presents the design of a Digital Beamformer (DBF) receiver for Synthetic Aperture Radar. Conventional SAR system design is constraint by the contradicting requirements of wider swath coverage and fine resolution to be achieved simultaneously. To overcome this, digital beamforming in SAR is introduced. The exponential growth in digital hardware and signal processing capabilities stimulates the development of radar systems. In this thesis, digital beamforming for SAR at the receiver side is described. A Parabolic reflector with feed array receives the signal separately from each feed element corresponding to a particular swath region. Further DBF is used in digital domain to combine signals to form a single range line. This technique improves the performance with high resolution and coverage, gain and SNR. Based on software codes, these digital systems are more flexible and easier to reconfigure than RF-hardware. Simulation of DBF receiver is performed on the HDL and MATLAB platform. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/8563 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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15MECV08.pdf | 15MECV08 | 2.1 MB | Adobe PDF | ![]() View/Open |
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