IP Verification at SoC Level

Abstract

In today’s regularly advancing technological world its very important for the manufacturer to achieve a very great quality in the minimum time, in short a good time to market is high on demand. The verification of design enacted makes it a very vital part to ensure the quality of product and to ensure a bug-free design when provided to the customer. Here this thesis work describe complete a verification flow from RTL to GLS with timing constraints. The synthesized gate level netlist is generated, which also has the influence of physical constraints and timing constraints, from RTL.Verification Plan is designed as per the functional equivalency understood from the design for verifying the system interconnect of SoC for master slave configuration. In SoC level most of the IP’s come under the category of the Black Box verification, which makes it very vital for the verification engineer to design strictly as per specifications provided by the IP owner. The verification plan is formed for CMU(Clock Monitor Unit) and the test-cases are developed as per the plan and the IP design constraints, to check the connectivity with the SoC environment, interconnects and access the core and develop the test to check its functionality which is major task..