Verification of ARM v8 Processor using Top Level Testcases

Abstract

In ASIC design , verification is an essential step in the development of any product.it ensures that the product as designed is the same as the product as intended,by applying the test signals to the design and check whether its matches with the golden output or not. verification is an essential step in the development of any product. Verification ensures that the product as designed is the same as the product as intended. Unfortunately, many design projects do not complete thorough design qualification resulting in products that do not meet customer expectations and require costly design modifications. More the complex is design , the verification of design is also more complex and verification time is also more.So to verify more corner cases easily , Random Instruction Sequence (RIS) is more effective approach . Most of design bugs are flushed out by the deterministic approach, RIS tools are also highly effective in hitting obscure cases.The tool uses template library that contains test-cases. A test file contains registers and memory values. Random test generator never generates a test which is not a valid test. A Translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location.so the second part is to analyse the TLB and how the address translation works.Thesis also contains invalidation of the TLB. and affected translation registers and attributes for the translation table walk and invalidation.