Verification of Hardware IP Blocks in the Domain of TCP/IP Networking

Abstract

According to Google estimation, total number of the active web pages as of today exceed 1 trillion. Similarly, the amount of data transmitted through social networks are also growing exponentially. As size of data is increasing in the systems involved in networking and packet processing, data center workloads demands power efficiency as well low cost.It is challenging to improve all factors simultaneously. To overcome this problem, customized application specific hardware accelerators are becoming integral parts of modern SoC architectures. To advance the capability of the Intel Xeon server, some of the OVS (Open Virtual Switch) functionalities (software functionalities) like classification of packet, forwarding information base lookup, key-actions, IPv6 extension headers, checksum, tunneling, were offloaded onto hardware (FPGA). FPGAs are tremendously enabling the new types of servers to execute bitwise operations in parallel. FPGA is placed along with Intel Xeon servers, accessible through PCIe or QPI. Accelerators complement CPU cores to meet market needs for throughput and performance, for the diverse workloads within the Data Center. Verification infrastructure was developed to validate the Networking IP Blocks involved in offloading of selected OVS functionalities like classification, lookup and tunneling. A memory model was developed to validate the functionality of standard interface protocols for communication within the infrastructure and to facilitate integration of IPs on Xeon server. Verification efforts were made towards automation and reduction of time involved in debugging. Verification efficiency was improved by making the IP level environment reusable, and by randomization of test scenarios. The thesis summarizes basic architecture of hardware accelerator, functional and performance verification models used to ensure the quality and reliability on the system.