Study Of Futuristic Approaches To Get Better QoR In Physical Implementation

Abstract

The quality of the netlist generated during synthesis has an enormous impact on the rest of the physical design flow. For SoC’s designed at advanced nodes, it is very essential to come out of synthesis with predictable timing and congestion estimates. The quality of the netlist coming out of synthesis has a big impact on the speed and predictability of the backend physical implementation. Optimizing at higher abstraction levels offer more room for QoR improvement, in addition to enabling faster runtimes. High quality physical RTL output makes the entire design flow more predictable with shorter design cycles. Along with this achieving timing closure in their first iteration is also a challenge. The design team must iterate by studying the output of the physical synthesis run, then potentially massage the input, e.g., by changing the floorplan, timing assertions, pin locations, logic structures, etc., in order to hopefully achieve a better solution for the next iteration. In this project we are studying the approaches to get better QoR in physical implementation. The first approach is to facilitate family integration to get floorplan definition early in the design cycle, in order to avoid major critical issues in the later stage of the design cycle. The second approach is using Synopsys Physical Guidance flow. This flow is jointly supported by DC and ICC to improve runtime, correlation and routability and to reduce routing related congestion.