Incremental Static Timing Analysis For Complex Design

Abstract

Performance Verification (PV) is the art of determining whether the circuit design behaves as expected or not. In which timing analysis plays an important role. It analyzes and solves timing problem to ensure that the design meets the required frequency. Generally Static Timing Analysis is used more often than Dynamic Timing Analysis because it consumes less time as compared to DTA and also eliminates the need of generating test vectors which can be a tedious job for a complex design. The biggest challenge in the layout edit in a design is that it requires whole performance verification (PV) cycle to be rerun which may consume a lot of time (even days). Incremental Static Timing Analysis is an effort made to reduce the time of PV cycle of a complex design during any layout edits. This incremental PV is an advanced version which tries to resolve this problem. The notion of incremental PV is to propagate changes in circuit timing / noise caused by an alteration in layout to only those parts of circuit that require it. The flow comprises of Incremental Extraction, Timing and Noise. The flow is capable of analyzing PV impact for following incremental layout edits; wire width and layer changes, wire movement, cell sizing, cell movement and addition or deletion of shields. The flow not only analyzes nets with layout edits but also reanalyzes nets in the vicinity of these edited nets.